The present invention relates to semiconductor memory devices, and more particularly to a self-refresh method and refresh control circuit for a semiconductor memory device function.
The refresh operation of memory cells should be continuously performed even in a stand-by mode so as to retain data stored in the memory cell, i.e., that of a Dynamic Random Access Memory (DRAM) device. A self-refresh mode is widely used for DRAMs. The self-refresh mode is of the type adapted to perform the refresh operation of the memory cell with the lapse of a predetermined time after going into an operation stand-by mode, even though a separate control signal is not applied from an external source to the memory device. Once the self-refresh mode starts, it is preferable to perform the refresh operation of all memory cells in order to keep data. Thus, the memory devices employing the self-refresh mode have their own refresh regulation time (i.e. the minimum time required in performing the self-refresh mode). Generally, the time required in refreshing data of all memory cells in the self-refresh mode approximates the time required in accessing data in all memory cells in a normal access mode. Preferably, the more the refresh regulation time approximates the time required in the normal access mode, that is, the shorter the refresh regulation time is, the more advantageous the memory device is, since more time can be assigned to the access operation.
In the widely used self-refresh mode, with the lapse of the predetermined time after going into a CBR (CAS before RAS) mode, sequential row addresses are internally generated until the CBR mode is completed and then word lines are activated, thereby refreshing data of the memory cells. FIG. 1 is a timing diagram showing an operation of such a self-refresh mode. Referring to FIG. 1, the memory device having N word lines and M bit lines performs the normal access mode according to row and column address signals X=0 Y=0, X=0 Y=1, X=0 Y=2, . . . X=N Y=M supplied externally. With the lapse of the predetermined time in the CBR mode, the normal access mode is converted to the self-refresh mode, thereby internally generating the sequential row addresses X=0, X=1, . . . X=N, so that the refresh operation of the memory cells is performed in the unit addressed by the word line. The memory cell requiring the longest time in completing the refresh operation in FIG. 1 will now be discussed. Assuming that time T1 is required in accessing data of all memory cells, the normal access mode is performed for nearly time T1 except that the memory cell designated by the last address defined as X=N Y=M, and thereafter the operation stand-by mode starts. Thereby, the self-refresh mode starts and then the refresh operation is performed for time T2 until internal row addresses of X=0, X=1, . . . X=N are generated. This indicates that the memory cell designated by the last address defined as X=N Y=M is refreshed with the lapse of time T1+T2. Accordingly, the refresh regulation time of the memory device having the timing diagram shown in FIG. 1 should be defined as time T1+T2 at least.
However, the memory device having the timing diagram shown in FIG. 1 has such a problem that the refresh regulation time becomes longer by time T1 than time T2 required in refreshing all memory cells. Since time T1 is generally set to be nearly equal to time T2, the refresh regulation time becomes twice as much as the necessary time.
In order to overcome the above problem, another conventional self-refresh method is shown in FIG. 2, which is capable of reducing the refresh regulation time by performing a burst refresh mode for a short time before and after the self-refresh mode. Referring to FIG. 2, after the normal access mode is performed for time T1, the burst refresh mode is performed in which the row address RAS is toggled at short intervals before going into the self-refresh mode, and thereby the word lines are sequentially activated for time T3 much shorter than time T1, so that all memory cells are refreshed. Thereafter, the normal self-refresh operation is performed for time T2. As CAS and RAS are disabled, the burst refresh mode is performed again after the self-refresh mode is completed, and then the normal access mode is performed. The refresh regulation time of the memory device having the refresh method shown in FIG. 2 is set to be the longer of T1+T3 or T2+T3. Since time T3 required in performing the burst refresh mode is set short enough to be ignored as compared to time T1 or T2, the refresh regulation time of this memory device can be defined as time T2 required in refreshing all memory cells. Thus, such a memory device has an advantage that the refresh regulation time can be shortened by half as compared to that of the memory device shown in FIG. 1.
However, in the method shown in FIG. 2, since RAS applied to the memory device should be toggled at short intervals in order to perform the burst refresh mode, the controller for driving the memory device must be able to perform the burst refresh mode.